Recently, the demand for small-sized large capacity non-volatile semiconductor memory devices has rapidly increased, above all, a NAND type flash memory that can be expected to be integrated on a large scale and massively stored by connecting a plurality of memory cells in series to compose a NAND cell block as compared with a conventional NOR type flash memory. The data program and erasure operations of the NAND type flash memory are as follows:
The data program operation of the NAND type flash memory is sequentially performed from a memory cell at the farthest position from a bitline. First, if the data program operation is started, 0V (“0” data programming) or a power supply voltage Vcc (“1” data programming) is applied to the bitline in response to the programming data, and Vcc is given to the selected gate line on the selected bitline side. In this case, when the bitline is at 0V, a channel part inside the NAND cell is fixed at 0V through the selected gate transistor in the connected selected NAND cell. When the bitline is at Vcc, after the channel part inside the NAND cell is charged by [Vcc-Vtsg] (however, Vtsg is the threshold voltage of the selected gate transistor) through the selected gate transistor, the channel part is in a floating state in the connected selected NAND cell. Subsequently, the voltage of a control gate line of the selected memory cell inside the selected NAND cell is increased from 0V to Vpp (=about 20V: high voltage for programming), and the voltage of a control gate line of the non-selected memory cell inside the selected NAND cell is increased from 0V to Vmg (=about 10V: intermediate voltage).
Here, when the bitline is at 0V, because the channel part inside the NAND cell is fixed at 0V in the connected selected NAND cell, a large potential difference is created across the gate (=Vpp potential) and the channel part (=0V) of the selected memory cell inside the selected NAND cell, electronic injection occurs from the channel part to the floating gate. This allows the threshold voltage of the selected memory cell to be shifted in a positive direction. This condition is a data “0”.
On the other hand, when the bitline is at Vcc, because the channel part inside the NAND cell is in a floating state in the connected selected NAND cell, a potential of the channel part in floating state as it stands is increased from the [Vcc-Vtsg] potential to a Vmch (=about 8V), accompanied with a voltage build-up (0V->Vpp, Vmg) of the control gate line by the affection of capacitive coupling between the control gate line and channel part inside the selected NAND cell. In this case, because a potential difference between the gate (=Vpp potential) and channel part (=Vmch) of the selected memory cell inside the selected NAND cell is relative small (about 12V), electronic injection never occurs, therefore, the threshold voltage of the selected memory cell remains unchanged and a negative condition is kept. This condition is a data “1”.
The data erasure of the NAND type flash memory is simultaneously performed on all the memory cells in the selected NAND cell block. Namely, all the control gates in the selected NAND cell block are fixed at 0V, the control gates and all the selected gates in the bitlines, source lines and non-selected NAND cell blocks are in a floating state, a high voltage of about 20V is applied to a p-type well (or p-type substrate). This releases electrons from the floating gates to the p-type well in all the memory cells inside the selected NAND cell block to shift the threshold voltage in a negative direction. Thus, the data erasure operation is designed to be performed by a block unit in batch in the NAND cell type flash memory.
The data read-out is performed by sensing whether or not current flows in the selected memory cell at a time when the voltage of the control gate in the selected memory cell is fixed at 0V, and the voltages (for example, 5V) of the control gates and selected gates in memory cells other than the former defined from stress at a time when read-out operation is performed on them are fixed.
Normally, the threshold voltage after the “0” data programming must be controlled in the scope of about 0V to about 4V. Therefore, re-programming data is set (verification by bit) so as to allow program verification to be performed, only memory cells in which “0” data programming is short to be sensed, and re-programming to be performed on only the memory cells in which “0” date programming is short. The memory cell in which “0” date programming is short is sensed by reading out the selected control gate at, for example, 0.5V (verification voltage) (verification read-out). Namely, if the threshold voltage of the memory cell is 0.5V or more with a margin to 0V, the current flows in the selected memory cell, and the shortage of “0” data programming is sensed. Program time is optimized to individual memory cells by performing data programming while repeating program operation and program verification, and the threshold voltage after “0” data programming is controlled in the scope of 0V to about 4V.
The operations of a conventional NAND flash memory as mentioned above are described in general, for example, in T. Tanaka, et al., “A Quick Intelligent Page-Programming Architecture and a Shielded Bitline Sensing Method for 3V-Only NAND Flash Memory”, J. Solid State Circuits, Vol. 29, No. 11, pp. 1366-1372, November, 1994.